| Process Criteria | Specification | |
| Normal | Special | |
| Min. Line/Spacing, external Layer | 4mil Over | 3mil below |
| Min. Line/Spacing, Internal Layer | 4mil Over | 3mil below |
| Min. Drilled Hole Size | 10mil | 8mil below |
| Aspect Ratio (Thickness to Min. Hole Diameter) | 10 | 20 |
| Land Size Internal (Diameter Over Drill) | Hole+0.3 | Hole+0.2 |
| Land Size External (Diameter Over Drill) | Hole+0.3 | Hole+0.2 |
| No-Connect (Diameter Over Drill) | 0.65 | |
| Plated Through Hole Tolerance | ±0.075 | ±0.05 |
| Min. Laser Via Hole | 0.127 | 0.05 |
| Laser Via Land Size (Diameter over Drill) | 0.25 | 0.150.05 |
| Min. Dielectric Thickness | 0.09 | 0.05 |
| Min. Core Thickness | 0.1 | 0.06T |
| Max. PCB Thickness | 4 | 5 |
| Thickness Tolerance(%) | 10% | 5% |
| Max. Board Dimensions | 580X480 | 580X700 |
| Bow and Twist (Through Hole - %) | 1% | 0.60% |
| Bow and Twist (SMT - %) | 1% | 0.60% |
| Min Conductor to Edge (When rout) | 0.3 | 0.15 |
| Min Conductor to Edge (When V-Cut) | 0.75 | 0.5 |
| Layer To Layer Registration Tolerance | 0.1 | 0.5 |
| Solder mask Clearance | 0.07 | 0.03 |
| Solder mask Dams | 0.075 | 0.04 |
| Impedance Tolerance(~ ohms +/- %) | 10% | 5% |
| Max. Layers | 24 | 28 |
| Max. Copper Weight Internal (Oz.) | 3OZ | 5OZ |
| Max. Copper Weight External (Oz.) | 3OZ | 10 OZ |
| Electrical Test Method | 100 Mil Grid , 70 Mil Grid , Flying Probe | |
| Materials | CEM-1 and CEM-3 , FR-4 , FR-4 High TG | |
| Polyimide , Teflon , Rogers , IS 680, FR-4 + Rogers , Metal Core , | ||
| Via Construction | Through Via , Blind and Buried Via , Laser Via (3+N+3) , copper pillar (4+N+4) | |
| Surface Finish | HSAL (Hot Solder Air Leveling ) , OSP (Organic Surface Protection) | |
| Immersion Tin Plating , Immersion Gold Plating , | ||
| Immersion Silver Plating , Electrolytic Gold Plating | ||